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| Data Sheet No. PD60259 ADVANCE INFORMATION IRS2453D(S)PbF SELF-OSCILLATING FULL-BRIDGE DRIVER IC Features Integrated 600V Full-Bridge Gate Driver CT, RT programmable oscillator 15.6V Zener Clamp on VCC Micropower Startup Logic Level Latched Shutdown Pin Non-latched shutdown on CT pin (1/6th VCC) Internal bootstrap FETs Excellent Latch Immunity on All Inputs & Outputs ESD Protection on All Pins 14-lead SOIC or PDIP package 1.0 usec (typ.) internal deadtime Description The IRS2453D is based on the popular IR2153 self-oscillating half-bridge gate driver IC, and incorporates a high voltage fullbridge gate driver with a front end oscillator similar to the industry standard CMOS 555 timer. HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise immunity is achieved with low di/dt peak of the gate drivers, and with a undervoltage lockout hysteresis greater than 1.5V. The IRS2453D also includes latched and non-latched shutdown pins. Package 14 Lead PDIP IRS2453DPbF 14 Lead SOIC (Narrow Body) IRS2453DSPbF Typical Connection Diagram + AC rectified line 15V 1 VCC VB1 14 IRS2453D 2 COM 3 CT 4 RT 5 SD 6 LO1 7 LO2 HO1 13 VS1 12 NC 11 VB2 10 HO2 9 VS2 8 LOAD - AC rectified line * Please note that this datasheet contains advanced information which could change before the product is released to production. 1 IRS2453DPbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB1, VB2 VS1, VS2 VHO1, VHO2 VLO1, VLO2 VRT VCT VSD IRT ICC dVS/dt PD PD RJA RJA TJ TS TL Parameter Definition High Side Floating Supply Voltage High Side Floating Supply Offset Voltage High-Side Floating Output Voltage Low-Side Output Voltage RT Pin Voltage CT Pin Voltage SD Pin Voltage RT Pin Current Supply Current (Note 1) Allowable Offset Voltage Slew Rate Maximum Power Dissipation @ TA +25C, 8-Pin DIP Maximum Power Dissipation @ TA +25C, 8-Pin SOIC Thermal Resistance, Junction to Ambient, 8-Pin DIP Thermal Resistance, Junction to Ambient, 8-Pin SOIC Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) Min. -0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 -0.3 -5 ---50 ---------55 -55 --- Max. 625 VB + 0.3 VB + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 5 25 50 1.0 0.625 125 200 150 150 300 Units V V V V V V V mA mA V/ns W W C/W C/W C Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. 2 IRS2453DPbF Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VBS1, VBS2 VS1, VS2 VCC ICC TJ Parameter Definition High Side Floating Supply Voltage Steady State High Side Floating Supply Offset Voltage Supply Voltage Supply Current Junction Temperature Min. VCC - 0.7 -3.0 (Note 2) VCCUV+ (Note 3) -25 Max. VCLAMP 600 VCLAMP 5 125 Units V V V mA C Note 2: Care should be taken to avoid output switching conditions where the VS node flies inductively below ground by more than 5V. Note 3: Enough current should be supplied to the VCC pin of the IC to keep the internal 15.6V zener diode clamping the voltage at this pin. Recommended Component Values Symbol RT CT Parameter Component Timing Resistor Value CT Pin Capacitor Value Min. 1 330 Max. ----- Units k pF VBIAS (VCC, VBS) = 14V, VS=0V and TA = 25C, CLO1=CLO2 = CHO1=CHO2 = 1nF. IRS2453D Frequency vs. RT 1000000 CT Values 100000 Frequency (Hz) 10000 1000 100 10 1000 330pf 470pF 1nF 2.2nF 4.7nF 10nF 10000 100000 1000000 RT (Ohm) 3 IRS2453DPbF Electrical Characteristics VBIAS (VCC, VBS) = 14V, CT = 1 nF and TA = 25C unless otherwise specified. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO1=CLO2=CHO1=CHO2=1nF. Symbol VCCUV+ VCCUVVCCUVHYS IQCCUV IQCC VCLAMP Definition Rising VCC Undervoltage Lockout Threshold Falling VCC Undervoltage Lockout Threshold VCC Undervoltage Lockout Hysteresis Micropower Startup VCC Supply Current Quiescent VCC Supply Current VCC Zener Clamp Voltage Min 10.0 8.0 1.6 ----14.6 Typ 11.0 9.0 2.0 140 1.3 15.6 Max 12.0 10.0 2.4 200 2.0 16.6 Units Test Conditions Low Voltage Supply Characteristics V A mA V ICC = 5mA VCC VCCUV- Floating Supply Characteristics IQBS1UV, IQBS2UV IQBS1, IQBS2 VBS1UV+, VBS2UV+ VBS1UV-, VBS2UV-, ILK1, ILK2 VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage negative Going Threshold Offset Supply Leakage Current 8.0 7.0 --9.0 8.0 --10.0 9.0 50 A VB = VS = 600V V Micropower Startup VBS Supply Current Quiescent VBS Supply Current ----3 60 10 100 A A VCC VCCUV-, VCC = VBS Oscillator I/O Characteristics fOSC d ICT ICTUV VCT+ VCTVRT+ VRTVRTUV Oscillator Frequency RT Pin Duty Cycle CT Pin Current UV-Mode CT Pin Pulldown Current Upper CT Ramp Voltage Threshold Lower CT Ramp Voltage Threshold High-Level RT Output Voltage, VCC - VRT Low-Level RT Output Voltage UV-Mode RT Output Voltage 19.6 89 48 --1 --------------20.2 95 50 0.05 5 9.1 4.8 10 100 10 100 0 20.8 101 52 1.0 ------50 300 50 300 100 % A mA V mV mV mV mV mV IRT = 100A IRT = 1mA IRT = 100A IRT = 1mA VCC VCCUVVCC = 7V kHz RT = 36.5k RT = 7.15k fo < 100kHz 4 IRS2453DPbF Electrical Characteristics VBIAS (VCC, VBS) = 14V, CT = 1 nF and TA = 25C unless otherwise specified. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO1=CLO2=CHO1=CHO2=1nF. Symbol Definition Min Typ Max Units Test Conditions Gate Driver Output Characteristics VOH VOL VOL_UV tr tf tsd td IO+ IOHigh-Level Output Voltage, VBIAS - VO Low-Level Output Voltage, VO UV-Mode Output Voltage, VO Output Rise Time Output Fall Time Shutdown Propagation Delay Output Deadtime (HO or LO) Output source current Output sink current ------------0.75 ----VCC COM COM 120 50 275 1.0 180 260 ------220 100 --1.50 ----sec mA nsec IO = 0A IO = 0A IO = 0A, VCC VCCUV- Shutdown VSD VCTSD VRTSD Shutdown Threshold at SD pin (latched) CT Voltage Shutdown Threshold (non latched) SD-Mode RT Output Voltage, VCC - VRT ------2.0 2.3 10 ----50 V V mV IRT = 100A, VCT = 0V --Bootstrap FET Characteristics VB1_ON VB2_ON IB1_CAP IB2_CAP IB1_10V IB2_10V 100 300 mV IRT = 1mA, VCT = 0V VB when the bootstrap FET is on VB source current when FET is on VB source current when FET is on --30 8 13.7 55 12 ----- V CBS=0.1uF mA --- VB=10V 5 IRS2453DPbF Lead Assignment 1 VCC 2 COM 3 CT 4 RT 5 SD 6 LO1 7 LO2 VB1 14 HO1 13 IRS2453D VS1 12 NC 11 VB2 10 HO2 9 VS2 8 Lead Definitions Lead Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol VCC COM CT RT SD LO1 LO2 VS2 HO2 VB1 NC VS1 HO1 VB1 IC power and signal ground Oscillator timing capacitor input Oscillator timing resistor input Shutdown input Low-side gate driver output Low-side gate driver output High voltage floating supply return High-side gate driver output High side gate driver floating supply No connect High voltage floating supply return High-side gate driver output High side gate driver floating supply Description Logic and internal gate drive supply voltage 6 IRS2453DPbF Functional Block Diagram RT 4 R + R R + R/2 SQ R1 R2 Q DEAD TIME 14 VB1 HV Level Shift Q PULSE FILTER R S 13 HO1 Q Q DEAD TIME PULSE 12 VS1 BOOTSTRAP DRIVE GEN S CT 3 R/2 + - DELAY 6 LO1 SD 5 2.0V S R Q HV Level Shift 10 VB2 Q PULSE FILTER R S 9 HO2 PULSE GEN 8 VS2 BOOTSTRAP DRIVE UV DETECT 15.4V DELAY 1 VCC 7 LO2 2 COM All values are typical. 7 IRS2453DPbF Timing Diagram VCC VCCUV+ Fault mode VCT<1/6*VCC 2/3 VCC 1/3 VCC 1/6 VCC VCC LO1 VCC LO2 VCC DT HO1 VCC DT DT HO2 VCC VRT 1mA IRT -1mA 8 IRS2453DPbF Functional Description Under-voltage Lock-Out Mode (UVLO) The under-voltage lockout mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. The IRS2453D under voltage lock-out is designed to maintain an ultra low supply current of less than 150uA, and to guarantee the IC is fully functional before the high and low side output drivers are activated. During under voltage lock-out mode, the high and low-side driver outputs LO1, LO2, HO1, HO2 are all low. With VCC above the VCCUV+ threshold, the IC turns on and the output begin to oscillate. Latched Shutdown When the SD pin is brought above 2V, the IC goes into fault mode and all outputs are low. VCC has to be recycled below VCCUV- to restart the IC. The SD pin can be used for overcurrent or over-voltage protection using appropriate external circuitry. 50% HO1 td_HO1 LO1 50% 50% td_LO1 Normal operating mode Once VCC reaches the start-up threshold VCCUV+, the MOSFET M1 opens, RT increases to approximately VCC (VCCVRT+) and the external CT capacitor starts charging. Once the CT voltage reaches VCT- (about 1/3 of VCC), established by an internal resistor ladder, LO1 and HO2 turn on with a delay equivalent to the deadtime td. Once the CT voltage reaches VCT+ (approximately 2/3 of VCC), LO1 and HO2 go low, RT goes down to approximately ground (VRT-), the CT capacitor starts discharging and the deadtime circuit is activated. At the end of the deadtime, LO2 and HO1 go high. Once the CT voltage reaches VCT-, LO2 and HO1 go low, RT goes to high again, the deadtime is activated. At the end of the deadtime, LO1 and HO2 go high and the cycle starts over again. The frequency is best determined by the graph, Frequency vs. RT, Page 3, for different values of CT. A first order approximate of the oscillator frequency can also be calculated by the following formula:: 50% ton_LO 50% Deadtime Waveform Definitions Deadtime waveform tr 90% HO LO tf 10% Rise and fall time waveform f 1 1.453 x RT x CT This equation can vary slightly from actual measurements due to internal comparator over- and under-shoot delays. Bootstrap MOSFET The internal bootstrap FET and supply capacitor (CBOOT) comprise the supply voltage for the high side driver circuitry. The internal boostrap FET only turns on when the corresponding LO is high. To guarantee that the high-side supply is charged up before the first pulse on HO1 and HO2, LO1 and LO2 are both on when CT ramps between zero and 1/3*VCC. LO1 and LO2 are also on when CT is grounded below 1/6*VCC to ensure that the bootstrap capacitor is charged when CT is brought back over 1/3*VCC. Non-latched Shutdown If CT is pulled down below VCTSD (approximately 1/6 of VCC) by an external circuit, CT doesn't charge up and oscillation stops. All outputs are held low and the bootstrap FETs are off. Oscillation will resume once CT is able to charge up again to VCT-. 9 IRS2453DPbF IRS2453D IRS2453DS 10 IRS2453DPbF Part number Sxxxxx YWW? ?XXXX Lot Code (Prod mode - 4 digit SPN code) IR logo Date code Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released Assembly site code Per SCOP 200-002 ORDER INFORMATION 8-lead PDIP: order IRS2453DPbF 8-lead SOICN: order IRS2453DSPbF 8-lead SOICN tape & reel: order IRS2453DSTRPbF Qualification: Industrial, MSL3, lead-free WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 3/27/2006 11 |
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